1. Field of the Invention
The present invention relates to multilayer capacitor greatly reducing the equivalent serial inductance (ESL) and production method thereof, more particularly relates to a multilayer capacitor used as a decoupling capacitor and manufacturing method thereof.
2. Description of the Related Art
In recent years, while advances have been made in reducing the voltage of power sources used for supplying power to large-scale integrated circuits (LSI's) and other integrated circuits, the load current has increased.
Therefore, it has become extremely difficult to keep fluctuations in the power source voltage to within tolerances when faced with rapid changes in the load current. Therefore, a decoupling capacitor (for example two-terminal structure multilayer ceramic capacitor) is now being connected to a power source. At the time of transitory fluctuation in the load current, current is supplied from this multilayer ceramic capacitor to the LSI of the central processing unit (CPU) etc. to suppress fluctuation of the power source voltage.
Along with the increasingly higher operating frequencies of today's CPU's, however, the fluctuations in the load current have become faster and larger. The equivalent serial inductance (ESL) of the decoupling capacitor itself now has a great impact on fluctuations of the power source voltage.
That is, since the ESL is high in a conventional multilayer ceramic capacitor, fluctuation of the power source voltage V easily becomes greater in the same way as above along with fluctuations in the load current i.
That is because the fluctuations in voltage at the time of transition of the load current are approximated by the following equation 1 and therefore the level of the ESL is related to the magnitude of fluctuation of the power source voltage. Further, from equation 1, reduction in the ESL can be said to be linked with stabilization of the power source voltage.dV=ESL·di/dt  equation 1
where,
dV is transitory fluctuation of voltage (V),
i is the fluctuation of current (A), and
t is the time of fluctuation (sec).
As a multilayer capacitor wherein the ESL is reduced, a multilayer capacitor shown in Japanese Unexamined Patent Publication No. 2003-51423 is known. According to this multilayer capacitor, parasitic inductance can be reduced. As a result, the ESL can be reduced. However, it has been required to further reducing the ESL.
In Japanese Unexamined Patent Publication No. 2006-60147, a two terminal capacitor is shown which comprises conductor layer of an internal layer portion, a dummy conductor layer sandwiching the internal layer portion in stacking direction. The dummy conductor layers, and the dummy conductor layer and terminal electrode are connected via metallic particles in dielectric layer. However, in the two terminal capacitor of the JP Unexamined Patent Publication No. 2006-60147, the effects of reducing the ESL cannot be obtained sufficiently because the metallic particles are used for preventing peeling of terminal electrodes.
Further, as a multilayer capacitor wherein the ESL is reduced, a multi-terminal multilayer capacitor shown in Japanese Unexamined Patent Publication No. 2002-299152 is known. In the multi-terminal multilayer capacitor, by increasing external terminal electrode, current flow varying in direction can be realized in an internal conductor layer. As a result, further reducing of the ESL becomes possible. However, in order to respond the increasingly higher operating frequencies of today's CPU's, in the multi-terminal capacitor, further reducing the ESL is required.